RDY never goes low to indicate that a conversion is complete. Here's how I'm connecting it on the bench,(includes recommended bypass caps (100n) on Vdd and VrefVref: 5vdcVin+: either GND, 3.3 or 5vVin-: GNDVss: GNDSCK: high (5v), steady stateSDO/RDY: moni..
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